1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a hemi-spherical grained (HSG) silicon film.
2. Description of the Related Art
Increasing the surface area of capacitor electrodes, narrowing the distance between the electrodes, and using a dielectric with a higher dielectric constant increase the capacitance of a capacitor.
A horizontal method and a vertical method are used for increasing the surface area of a capacitor electrode. Between the two methods, horizontal increase of the surface area of an electrode is less desirable because this method limits high integration of semiconductor devices. In contrast, the vertical method, which forms the electrode three-dimensionally, reduces horizontal surface area of the electrode and increases vertical surface area of the electrode. A stack type electrode, a fin type electrode, and a cylindrical type electrode are representative three-dimensional electrodes.
In other words, the vertical method has an advantage in that the surface area of the electrode increases without limiting integration of semiconductor devices. However, the vertical method causes a problem in planarization due to a large step height difference between the area containing the electrode and the surrounding area.
Forming a HSG silicon film on the electrode can solve above planarization problem. A conventional method of forming an HSG silicon film on the surface of the electrode increases the surface area of the electrode, maintaining the height of the electrode of a capacitor at an appropriate level.
Hereinafter, the conventional method of forming the HSG silicon film of the semiconductor device is described with reference to the attached drawings.
Referring to FIG. 1, an etch stopper layer 12 is formed on the entire surface of a semiconductor substrate 10, and a polysilicon layer 14 is formed on the entire surface of etch stopper layer 12. Then, a patterned photosensitive layer 16 for masking an area of polysilicon layer 14 is formed on polysilicon layer 14. Polysilicon layer 14 is anisotropically etched using patterned photosensitive layer 16 as an etching mask. Anisotropic etching continues until etch stopper layer 12 under polysilicon layer 14 is exposed. After removal of patterned photosensitive film 16, as shown in FIG. 2, a polysilicon layer pattern 14a remains on etch stopper layer 12. Polysilicon layer pattern 14a is used as a storage node. A polymer layer (not shown) forms as a by-product of the anisotropic etching of polysilicon layer 14. This polymer layer can be removed by a hydrogen fluoride (HF) treatment before the removal of patterned photosensitive layer 16.
The process of removing patterned photosensitive layer 16 can be divided into an ashing step and a stripping step. The ashing step burns patterned photosensitive layer 16 using plasma, and the stripping step removes the ashes. In the ashing, a reaction between plasma and patterned photosensitive layer 16 produces a polymer layer 18 on the side wall of patterned polysilicon layer 14a.
After the stripping step, source gases such as SiH.sub.4 and Si.sub.2 H.sub.6 form HSG seeds on the entire surface of patterned polysilicon layer 14a. Then, the HSG seeds are grown by heating the semiconductor substrate, on which the HSG seeds are formed, and produce, as shown in FIG. 3, an HSG silicon layer 20 on patterned polysilicon layer 14a.
However, polymer layer 18 can prevent a uniform formation of the HSG seeds on patterned polysilicon layer pattern 14a. As a result, HSG silicon layer 20 lacks uniformity, as shown in FIG. 3. Namely, the morphology of HSG film 20 on patterned polysilicon layer 14a can be significantly different from the morphology of HSG film 20 on another patterned polysilicon layer 14a, and thereby, each storage node can have a different electrostatic capacity. In addition, there is a chance that a portion of patterned polysilicon layer pattern 14a is not covered with HSG film 20.